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| SI4410DY N-channel TrenchMOS logic level FET Rev. 03 -- 4 December 2009 Product data sheet 1. Product profile 1.1 General description Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product is designed and qualified for use in computing, communications, consumer and industrial applications only. 1.2 Features and benefits Low conduction losses due to low on-state resistance Suitable for high frequency applications due to fast switching characteristics 1.3 Applications DC motor control DC-to-DC convertors Lithium-ion battery applications Notebook computers Portable equipment 1.4 Quick reference data Table 1. VDS ID Ptot Quick reference Conditions Tamb = 25 C; pulsed; see Figure 1 and 3 Tamb = 25 C; pulsed; see Figure 2 VGS = 10 V; ID = 10 A; VDS = 15 V; Tj = 25 C; see Figure 12 VGS = 4.5 V; ID = 5 A; Tj = 25 C; see Figure 10 and 11 VGS = 10 V; ID = 10 A; Tj = 25 C; see Figure 10 and 11 Min Typ Max 30 10 2.5 Unit V A W drain-source voltage Tj 25 C; Tj 150 C drain current total power dissipation gate-drain charge Symbol Parameter Dynamic characteristics QGD 7 nC Static characteristics RDSon drain-source on-state resistance 15 20 m - 11 13.5 m NXP Semiconductors SI4410DY N-channel TrenchMOS logic level FET 2. Pinning information Table 2. Pin 1 2 3 4 5 6 7 8 S S S G D D D D Pinning information Symbol Description source source source gate drain drain drain drain 1 4 mbb076 Simplified outline 8 5 Graphic symbol D G S SOT96-1 (SO8) 3. Ordering information Table 3. Ordering information Package Name SI4410DY SO8 Description plastic small outline package; 8 leads; body width 3.9 mm Version SOT96-1 Type number 4. Limiting values Table 4. Symbol VDS VGS ID Limiting values Parameter drain-source voltage gate-source voltage drain current Tamb = 70 C; pulsed; see Figure 1 Tamb = 25 C; pulsed; see Figure 1 and 3 IDM Ptot peak drain current total power dissipation tp 10 s; Tamb = 25 C; pulsed; see Figure 3 Tamb = 70 C; pulsed; see Figure 2 Tamb = 25 C; pulsed; see Figure 2 Tstg Tj IS storage temperature junction temperature source current Tamb = 25 C; pulsed Conditions Tj 25 C; Tj 150 C Min -20 -55 -55 Max 30 20 8 10 50 1.6 2.5 150 150 2.3 Unit V V A A A W W C C A In accordance with the Absolute Maximum Rating System (IEC 60134). Source-drain diode SI4410DY_3 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 -- 4 December 2009 2 of 12 NXP Semiconductors SI4410DY N-channel TrenchMOS logic level FET 120 Ider (%) 80 03aa19 120 Pder (%) 80 03aa11 40 40 0 0 50 100 150 200 Tamb (C) 0 0 50 100 150 200 Tamb (C) Fig 1. Normalized continuous drain current as a function of ambient temperature Fig 2. Normalized total power dissipation as a function of ambient temperature 03ae23 102 ID (A) 10 RDSon = VDS/ID tp = 10 s 1 ms 10 ms 1 P = tp T 100 ms D.C. 10-1 tp t T 10 s 10-2 10-1 1 10 VDS (V) 102 Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage SI4410DY_3 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 -- 4 December 2009 3 of 12 NXP Semiconductors SI4410DY N-channel TrenchMOS logic level FET 5. Thermal characteristics Table 5. Symbol Rth(j-sp) Rth(j-a) Thermal characteristics Parameter thermal resistance from junction to solder point thermal resistance from mounted on a printed-circuit board; junction to ambient minimum footprint; tp 10 s; see Figure 4 Conditions Min Typ Max 50 Unit K/W K/W 102 03ad49 Zth(j-amb) (K/W) 10 = 0.5 0.2 0.1 0.05 0.02 1 10-1 single pulse P = tp T tp T t 10-2 10-4 10-3 10-2 10-1 1 10 102 tp (s) 103 Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration SI4410DY_3 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 -- 4 December 2009 4 of 12 NXP Semiconductors SI4410DY N-channel TrenchMOS logic level FET 6. Characteristics Table 6. Symbol VGS(th) IDSS IGSS RDSon Characteristics Parameter gate-source threshold voltage drain leakage current gate leakage current drain-source on-state resistance Conditions ID = 250 A; VDS= VGS; Tj = 25 C; see Figure 9 VDS = 30 V; VGS = 0 V; Tj = 25 C VDS = 30 V; VGS = 0 V; Tj = 55 C VGS = 20 V; VDS = 0 V; Tj = 25 C VGS = -20 V; VDS = 0 V; Tj = 25 C VGS = 4.5 V; ID = 5 A; Tj = 25 C; see Figure 10 and 11 VGS = 10 V; ID = 10 A; Tj = 25 C; see Figure 10 and 11 IDSon on-state drain-source current total gate charge VDS 5 V; VGS = 10 V Min 1 20 Typ 15 11 Max 1 25 100 100 20 13.5 Unit V A A nA nA m m A Static characteristics Dynamic characteristics QG(tot) ID = 10 A; VDS = 15 V; VGS = 5 V; Tj = 25 C; see Figure 12 ID = 10 A; VDS = 15 V; VGS = 10 V; Tj = 25 C; see Figure 12 VDS = 25 V; RL = 25 ; VGS = 10 V; RG(ext) = 6 ; Tj = 25 C VDS = 15 V; ID = 10 A; Tj = 25 C; see Figure 13 IS = 2.3 A; VGS = 0 V; Tj = 25 C; see Figure 14 IS = 2.3 A; dIS/dt = -100 A/s; VGS = 0 V; VDS = 25 V; Tj = 25 C 21.5 40 8 7 13.5 9 70 30 34 34 60 30 20 100 80 nC nC nC nC ns ns ns ns S QGS QGD td(on) tr td(off) tf gfs gate-source charge gate-drain charge turn-on delay time rise time turn-off delay time fall time transfer conductance Source-drain diode VSD trr source-drain voltage reverse recovery time 0.7 50 1.1 80 V ns SI4410DY_3 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 -- 4 December 2009 5 of 12 NXP Semiconductors SI4410DY N-channel TrenchMOS logic level FET 50 ID (A) 10 V 5V 03ad50 50 ID (A) 40 VDS > ID x R DSon 03ad52 3.8 V 3.6 V 3.4 V 40 30 3.2 V 30 20 3V 2.8 V VGS = 2.6 V 20 10 10 Tj = 150 C 25 C 0 0 0 0.5 1 VDS (V) 1.5 0 1 2 3 VGS (V) 4 Fig 5. Output characteristics: drain current as a function of drain-source voltage; typical values 03aa36 Fig 6. Transfer characteristics: drain current as a function of gate-source voltage; typical values 03ad54 10-1 ID (A) 10-2 104 C (pF) 10-3 min 10-4 Coss typ max 103 Ciss 10-5 Crss 10-6 0 1 2 VGS (V) 3 10 10-1 1 10 VDS (V) 102 Fig 7. Sub-threshold drain current as a function of gate-source voltage Fig 8. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values SI4410DY_3 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 -- 4 December 2009 6 of 12 NXP Semiconductors SI4410DY N-channel TrenchMOS logic level FET 2.5 VGS(th) (V) 2 max 03aa33 0.03 RDSon () Tj = 25 C VGS = 3.2 V 3.4 V 03ad51 3.6 V 3.8 V 0.02 1.5 typ 4.5 V 5V 1 min 0.01 10 V 0.5 0 -60 0 0 60 120 Tj (C) 180 0 10 20 30 40 ID (A) 50 Fig 9. Gate-source threshold voltage as a function of junction temperature 2 a 1.5 03ad57 Fig 10. Drain-source on-state resistance as a function of drain current; typical values 10 VGS (V) 8 03ad55 ID = 10 A VDD = 15 V Tj = 25 C 6 1 4 0.5 2 0 -60 0 0 60 120 Tj (C) 180 0 10 20 30 QG (nC) 40 Fig 11. Normalized drain-source on-state resistance factor as a function of junction temperature Fig 12. Gate-source voltage as a function of gate charge; typical values SI4410DY_3 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 -- 4 December 2009 7 of 12 NXP Semiconductors SI4410DY N-channel TrenchMOS logic level FET 40 gfs (S) 30 Tj = 25 C VDS > ID x RDSon 03ae24 50 IS (A) 40 03ad53 VGS = 0 V 150 C 20 30 20 10 10 150 C 0 0 10 20 30 40 ID (A) 50 Tj = 25 C 0 0 0.4 0.8 1.2 VSD (V) 1.6 Fig 13. Forward transconductance as a function of drain current; typical values Fig 14. Source current as a function of source-drain voltage; typical values SI4410DY_3 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 -- 4 December 2009 8 of 12 NXP Semiconductors SI4410DY N-channel TrenchMOS logic level FET 7. Package outline SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 D E A X c y HE vMA Z 8 5 Q A2 pin 1 index Lp 1 4 A1 (A 3) A L wM detail X e bp 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 1.75 0.069 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 5.0 4.8 0.20 0.19 E (2) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) 0.7 0.3 0.028 0.012 o 0.010 0.057 0.004 0.049 0.019 0.0100 0.014 0.0075 0.244 0.039 0.028 0.041 0.228 0.016 0.024 8 o 0 Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT96-1 REFERENCES IEC 076E03 JEDEC MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 15. Package outline SOT96-1 (SO8) SI4410DY_3 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 -- 4 December 2009 9 of 12 NXP Semiconductors SI4410DY N-channel TrenchMOS logic level FET 8. Revision history Table 7. Revision history Release date 20091204 Data sheet status Product data sheet Change notice Supersedes SI4410DY-02 Document ID SI4410DY_3 Modifications: * * The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Product specification Product specification SI4410DY-01 - SI4410DY-02 SI4410DY-01 20010705 20010220 SI4410DY_3 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 -- 4 December 2009 10 of 12 NXP Semiconductors SI4410DY N-channel TrenchMOS logic level FET 9. Legal information 9.1 Data sheet status Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URLhttp://www.nxp.com. 9.2 Definitions Draft-- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet-- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Applications-- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Quick reference data-- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Limiting values-- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale-- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published athttp://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license-- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control-- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 9.3 Disclaimers General-- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes-- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use-- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. 9.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. TrenchMOS-- is a trademark of NXP B.V. 10. Contact information For more information, please visit:http://www.nxp.com For sales office addresses, please send an email to:salesaddresses@nxp.com SI4410DY_3 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 -- 4 December 2009 11 of 12 NXP Semiconductors SI4410DY N-channel TrenchMOS logic level FET 11. Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 9.1 9.2 9.3 9.4 10 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General description . . . . . . . . . . . . . . . . . . . . . .1 Features and benefits . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Quick reference data . . . . . . . . . . . . . . . . . . . . .1 Pinning information . . . . . . . . . . . . . . . . . . . . . . .2 Ordering information . . . . . . . . . . . . . . . . . . . . . .2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2 Thermal characteristics . . . . . . . . . . . . . . . . . . .4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . .9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . .10 Legal information. . . . . . . . . . . . . . . . . . . . . . . . 11 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Contact information. . . . . . . . . . . . . . . . . . . . . . 11 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 4 December 2009 Document identifier: SI4410DY_3 |
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